Microcontroller:
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. The Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. It also provides 32 I/O lines, 128bytes of RAM for data storage.
Features
Compatible with MCS-51™ Products
4K Bytes of In-System Reprogrammable Flash Memory
Endurance: 1,000 Write/Erase Cycles
Fully Static Operation: 0 Hz to 24 MHz
Three-level Program Memory Lock
128 x 8-bit Internal RAM
32 Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources
Programmable Serial Channel
Low-power Idle and Power-down Modes
4v to 5.5v operating range.
Extensive Boolean processing capability (single bit logic).
ISP (In system programming) using standard Vcc power supply.
DESCRIPTION OF ARCHITECTURAL STRUCTURE OF AT89C51
MEMORY ORGANISATION:
MCS-51 devices have a separate address space for program and data memory up to 64k bytes each of external program and data memory can be addressed.
PROGRAM MEMORY:
If the EA pin is connected to GND, all program fetches are directed to external memory. In the AT89C51RC if EA is connected to Vcc, program fetches the addresses 0000H through 7FFFH are directed to internal memory and fetches to addresses memory.
DATA MEMORY:
The AT89C51RC has internal data memory that is mapped into four separate segments. The lower 128 bytes of RAM, upper 128 bytes special function register (SFR) and 256 bytes expanded RAM (ERAM).
The four segments are :
The lower 128bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable.
The upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.
The special function registers, (SFR’s) (addresses 80H to FFH) are directly addressable only.
256 bytes expanded RAM (ERAM, 00H-FFH) is indirectly accessed by MOVX instruction and with the EXTRAM bit cleared.
Either direct or indirect addressing can access the lower 128 bytes. The upper 128 bytes can be accessed indirect addressing only. The upper 128 bytes occupy the same address but are physically separate from the SFR space. When an instruction accesses an internal location above address 7FH, the CPU knows whether the accesses is to the upper 128 bytes of data RAM or to SFR space by the direct addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For example MOV OAOH, #data.
SFR (SPECIAL FUNCTION REGISTER:
A map of the on-chip memory area is called the special function registers (SFR) space. Note that in the SFR's not all the addresses are occupied. Unoccupied addresses are not implemented on the chip. Read accesses to these addresses will in general return random data and write accesses will have no-effect. The functions of SFR's are described as follows:
ACCUMULATOR:
Acc is the accumulator register. The mnemonics for accumulator, specific Instructions. However, refer to the accumulator simply as "A".
B REGISTER:
The B register is used during multiply and divide operations for other instructions it can be treated as another scratch pad register.
PSW (PROGRAM STATUS REGISTER):
The PSW contains several status bits that reflect the current state of the cpu.the psw resides in the SFR space.
STACK POINTER:
This is of 8-bit wide. It is incremented before data is stored during PUSH and CALL executions.while the stack pointer may any where in on_chip RAM the stack pointer is initialized to 07h after a reset.this causes the stack to begin at location 08h.
DATA POINTER (DPTR):
This consists of a high type and a low byte. Its intended function is to hold a 16-bit address.it may be manipulated as a 16-bit register or as two independent 8-bit registers.
PORTS 0 TO 3:
P0, P1, P2, and P3 are the SFR of ports 0,1,2 & 3 respectively.writing a one of a port SFR causes the port output pin to switch low.when used as an input, the external state of a pin will be held in the port SFR.
SERIAL DATA BUFFER:
The serial buffer is actually two separate registers transmit buffer and a receive buffer.when data is involved to SBUF.It goes to transmit buffer and is held for serial transmission.when data is moved from SBUF.It comes from SBUF.It comes the receive buffer.
TIMER REGISTER BASIC TO 89C51:
Register pins (TH0, TL0) AND (TH1, TL1) are 16-bit counting registers for timer/counters 0&1, respectively.
CONTROL REGISTER FOR THE 89C51:
SFR, IP, IE, TMOD, SCON and PCON contain and status bits for the interrupt system.the timer/counters and the serial port.
INSTRUCTION SET:
The 89C51 instruction set has 111 instruction.it includes
Arithmetic
Logical
Data transfer
Boolean and
Branching instructions
ADDRESSING MODES:
There are five addressing modes in the 89C51 instruction set explained as follows:
Direct addressing
Indirect addressing
Register instructions
Immediate addressing
Indexed addressing
SERIAL INTERFACE:
The serial port is full duplex. It is also receive buffered. The serial port receive and transmit registers are both accessed at a special function register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register.
The serial port can operate in four modes:
MODE 0: Serial data enters and exits through RXD; TXD outputs the shift clock 8 bits are transmitted / received ( lsb first). The baud rate is fixed at 1/12 the oscillator frequency.
MODE 1: 10 bits are transmitted or received; a start bit (0), 8 data bits, and a stop bit (1), on receive the stop bit goes into RBB in special function register SCON. The baud rate is variable.
MODE 2: 11 bits are transmitted or received; a start bit (0), 8 bits, a programmable 8th data bit, and a stop bit (1). On transmit; the 9th data bit can be assigned the value of 0 or 1.
MODE 3: 11 bits are transmitted or received; a start bit (0), 8 data bits, a programmable 9th data bit, and a stop bit (1). In fact MODE 3 is the same as MODE 2 in all aspects expects baud rate. The baud rate in
MODE 3 is variable.
INTERRUPT SOURCES:
The AT89C51 has a total of six interrupt vector; two external interrupts, three timer interrupts, and the serial port interrupt. These interrupts are all shown in figure 4.1.2. Each of these can be individually enabled or disabled by setting or clearing a bit SFR, IE. IE also contains a global disable bit, EA, which disables all interrupts at once.
OSCILLATOR CHARACTERISTICS:
XTAL1 and XTAL2 are the input and output respectively, of an inverting amplifier, which can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used.
Temperature sensor:
The LM35 series are precision integrated circuit temperature sensors, whose output voltage is linearly proportional to the Celsius (Centigrade) temperature. The LM35 thus has advantage over linear temperature sensors calibrated in Kelvin, as the user is not required to subtract a large constant voltage from its output to obtain convenient centigrade scaling. The LM35 does not require any external calibration or trimming to provide typical accuracies over a full –55degree to +150degree C temperature range. The LM35's low output impedance, linear output and precise inherent calibration make interfacing to readout or control circuitry especially easy. It can be used with single power supplies or with plus and minus supplies.
The LM35DZ is rated to operate over a 0 to +100degree Celsius temperature range. The LM35 series is available packaged in hermetic TO-46 transistor packages, while the LM35D are also available in the plastic TO-92 transistor package. The LM35D is also available in an 8-lead surface mount small outline package and a plastic TO-202 package.
Features
Calibrated directly in degree Celsius (Centigrade)
Linear a 10.0 mV/ degree C scale factor
0.5degree C accuracy guarantee able (at +25 degree C)
Rated for full -55 degree to +150 degree C range
Suitable for remote applications
Low cost due to wafer-level trimming
Operates from 4 to 30 volts
Less than 60uA current drain
Low self-heating, 0.08 degree C in still air
Low impedance output, 0.1 ohm for 1mA load
The ADC0808 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter,8-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can directly access any of 8-single-ended analog signals. Easy interfacing to microprocessors is provided by the latched and decoded multiplexer address inputs and latched TTL TRI-STATE outputs. The design of the ADC0808 has been optimized by incorporating the most desirable aspects of several A/Conversion techniques. The ADC0808 offers high-speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device ideally suited to applications from process and machine control to consumer and automotive applications.
Phototransistor:
Phototransistor circuits may be adjusted for a selected sensitivity range and often do not require additional amplification. They can be applied in two modes, Active or Switch mode. In our project we have used SD3443 silicon NPN phototransistor.
The current will switch on or switch off the transistor indicates the presence or absence of object. When there is no light the current phototransistor is zero. Transistor will be in off condition, since IB=0.In this condition the collector voltage is maximum and is equal to vcc.when light falls on the base of the transistor develops proportional current which biases the transistor and allows it to conduct.
LCD display:
An LCD allows our application to output very specific messages to the user, making the application much more user friendly and impressive, which display the status messages of the device. In our project we have used 2*16 matrix LCD.It consists 16 pins, which is explained as follows.
Vcc, Vss and Vee: Vcc and Vss provide +5v and ground respectively .Vee is used for controlling LCD contrast.
RS (Register select): There are two very important register inside the LCD.The RS pin is used for their selection. If RS=0, the instruction command code register is selected, allowing the user to send a command such as clear display, cursor etc.If RS=1, the data register is selected allowing the user to send data to be displayed on the LCD.
R/W (read/write): R/W input allows the user to write information to the LCD or read information from it.R/W=1 when reading; R/W=0 when writing.
E (enable): The enable pin is used by the LCD to latch information presented to its data pins.
D0_D7: The 8_bit data pins D0_D7, are used to send information to the LCD or read the contents of the LCD’s internal registers.
Vcc and Vss: Vcc and Vss provide +5v and ground respectively for back light of LCD.
Circuit Description:
The circuit diagram is as shown in the figure 5.1.It consists of five nodes. Each node perform its own function using can protocol. Here port pin 2.0 of microcontroller of each node is connected to can bus.
The AT89C51 microcontroller is the master of the project. it controls the function of the can bus,sensors,switches and visual indicators. The crystal of 12MHz is connected along with the capacitor as shown in the circuit so as to provide the clock to the controller.
Working of each node is explained as follows
Object sensing controller:
Port pin p0.0 of microcontroller is connected to object sensor i.e. SD3443. Whenever it senses the object, sends the data frame with identifier msg2 to dashboard and compressor node to get activate.
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. The Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. It also provides 32 I/O lines, 128bytes of RAM for data storage.
Features
Compatible with MCS-51™ Products
4K Bytes of In-System Reprogrammable Flash Memory
Endurance: 1,000 Write/Erase Cycles
Fully Static Operation: 0 Hz to 24 MHz
Three-level Program Memory Lock
128 x 8-bit Internal RAM
32 Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources
Programmable Serial Channel
Low-power Idle and Power-down Modes
4v to 5.5v operating range.
Extensive Boolean processing capability (single bit logic).
ISP (In system programming) using standard Vcc power supply.
DESCRIPTION OF ARCHITECTURAL STRUCTURE OF AT89C51
MEMORY ORGANISATION:
MCS-51 devices have a separate address space for program and data memory up to 64k bytes each of external program and data memory can be addressed.
PROGRAM MEMORY:
If the EA pin is connected to GND, all program fetches are directed to external memory. In the AT89C51RC if EA is connected to Vcc, program fetches the addresses 0000H through 7FFFH are directed to internal memory and fetches to addresses memory.
DATA MEMORY:
The AT89C51RC has internal data memory that is mapped into four separate segments. The lower 128 bytes of RAM, upper 128 bytes special function register (SFR) and 256 bytes expanded RAM (ERAM).
The four segments are :
The lower 128bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable.
The upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.
The special function registers, (SFR’s) (addresses 80H to FFH) are directly addressable only.
256 bytes expanded RAM (ERAM, 00H-FFH) is indirectly accessed by MOVX instruction and with the EXTRAM bit cleared.
Either direct or indirect addressing can access the lower 128 bytes. The upper 128 bytes can be accessed indirect addressing only. The upper 128 bytes occupy the same address but are physically separate from the SFR space. When an instruction accesses an internal location above address 7FH, the CPU knows whether the accesses is to the upper 128 bytes of data RAM or to SFR space by the direct addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For example MOV OAOH, #data.
SFR (SPECIAL FUNCTION REGISTER:
A map of the on-chip memory area is called the special function registers (SFR) space. Note that in the SFR's not all the addresses are occupied. Unoccupied addresses are not implemented on the chip. Read accesses to these addresses will in general return random data and write accesses will have no-effect. The functions of SFR's are described as follows:
ACCUMULATOR:
Acc is the accumulator register. The mnemonics for accumulator, specific Instructions. However, refer to the accumulator simply as "A".
B REGISTER:
The B register is used during multiply and divide operations for other instructions it can be treated as another scratch pad register.
PSW (PROGRAM STATUS REGISTER):
The PSW contains several status bits that reflect the current state of the cpu.the psw resides in the SFR space.
STACK POINTER:
This is of 8-bit wide. It is incremented before data is stored during PUSH and CALL executions.while the stack pointer may any where in on_chip RAM the stack pointer is initialized to 07h after a reset.this causes the stack to begin at location 08h.
DATA POINTER (DPTR):
This consists of a high type and a low byte. Its intended function is to hold a 16-bit address.it may be manipulated as a 16-bit register or as two independent 8-bit registers.
PORTS 0 TO 3:
P0, P1, P2, and P3 are the SFR of ports 0,1,2 & 3 respectively.writing a one of a port SFR causes the port output pin to switch low.when used as an input, the external state of a pin will be held in the port SFR.
SERIAL DATA BUFFER:
The serial buffer is actually two separate registers transmit buffer and a receive buffer.when data is involved to SBUF.It goes to transmit buffer and is held for serial transmission.when data is moved from SBUF.It comes from SBUF.It comes the receive buffer.
TIMER REGISTER BASIC TO 89C51:
Register pins (TH0, TL0) AND (TH1, TL1) are 16-bit counting registers for timer/counters 0&1, respectively.
CONTROL REGISTER FOR THE 89C51:
SFR, IP, IE, TMOD, SCON and PCON contain and status bits for the interrupt system.the timer/counters and the serial port.
INSTRUCTION SET:
The 89C51 instruction set has 111 instruction.it includes
Arithmetic
Logical
Data transfer
Boolean and
Branching instructions
ADDRESSING MODES:
There are five addressing modes in the 89C51 instruction set explained as follows:
Direct addressing
Indirect addressing
Register instructions
Immediate addressing
Indexed addressing
SERIAL INTERFACE:
The serial port is full duplex. It is also receive buffered. The serial port receive and transmit registers are both accessed at a special function register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register.
The serial port can operate in four modes:
MODE 0: Serial data enters and exits through RXD; TXD outputs the shift clock 8 bits are transmitted / received ( lsb first). The baud rate is fixed at 1/12 the oscillator frequency.
MODE 1: 10 bits are transmitted or received; a start bit (0), 8 data bits, and a stop bit (1), on receive the stop bit goes into RBB in special function register SCON. The baud rate is variable.
MODE 2: 11 bits are transmitted or received; a start bit (0), 8 bits, a programmable 8th data bit, and a stop bit (1). On transmit; the 9th data bit can be assigned the value of 0 or 1.
MODE 3: 11 bits are transmitted or received; a start bit (0), 8 data bits, a programmable 9th data bit, and a stop bit (1). In fact MODE 3 is the same as MODE 2 in all aspects expects baud rate. The baud rate in
MODE 3 is variable.
INTERRUPT SOURCES:
The AT89C51 has a total of six interrupt vector; two external interrupts, three timer interrupts, and the serial port interrupt. These interrupts are all shown in figure 4.1.2. Each of these can be individually enabled or disabled by setting or clearing a bit SFR, IE. IE also contains a global disable bit, EA, which disables all interrupts at once.
OSCILLATOR CHARACTERISTICS:
XTAL1 and XTAL2 are the input and output respectively, of an inverting amplifier, which can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used.
Temperature sensor:
The LM35 series are precision integrated circuit temperature sensors, whose output voltage is linearly proportional to the Celsius (Centigrade) temperature. The LM35 thus has advantage over linear temperature sensors calibrated in Kelvin, as the user is not required to subtract a large constant voltage from its output to obtain convenient centigrade scaling. The LM35 does not require any external calibration or trimming to provide typical accuracies over a full –55degree to +150degree C temperature range. The LM35's low output impedance, linear output and precise inherent calibration make interfacing to readout or control circuitry especially easy. It can be used with single power supplies or with plus and minus supplies.
The LM35DZ is rated to operate over a 0 to +100degree Celsius temperature range. The LM35 series is available packaged in hermetic TO-46 transistor packages, while the LM35D are also available in the plastic TO-92 transistor package. The LM35D is also available in an 8-lead surface mount small outline package and a plastic TO-202 package.
Features
Calibrated directly in degree Celsius (Centigrade)
Linear a 10.0 mV/ degree C scale factor
0.5degree C accuracy guarantee able (at +25 degree C)
Rated for full -55 degree to +150 degree C range
Suitable for remote applications
Low cost due to wafer-level trimming
Operates from 4 to 30 volts
Less than 60uA current drain
Low self-heating, 0.08 degree C in still air
Low impedance output, 0.1 ohm for 1mA load
The ADC0808 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter,8-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can directly access any of 8-single-ended analog signals. Easy interfacing to microprocessors is provided by the latched and decoded multiplexer address inputs and latched TTL TRI-STATE outputs. The design of the ADC0808 has been optimized by incorporating the most desirable aspects of several A/Conversion techniques. The ADC0808 offers high-speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device ideally suited to applications from process and machine control to consumer and automotive applications.
Phototransistor:
Phototransistor circuits may be adjusted for a selected sensitivity range and often do not require additional amplification. They can be applied in two modes, Active or Switch mode. In our project we have used SD3443 silicon NPN phototransistor.
The current will switch on or switch off the transistor indicates the presence or absence of object. When there is no light the current phototransistor is zero. Transistor will be in off condition, since IB=0.In this condition the collector voltage is maximum and is equal to vcc.when light falls on the base of the transistor develops proportional current which biases the transistor and allows it to conduct.
LCD display:
An LCD allows our application to output very specific messages to the user, making the application much more user friendly and impressive, which display the status messages of the device. In our project we have used 2*16 matrix LCD.It consists 16 pins, which is explained as follows.
Vcc, Vss and Vee: Vcc and Vss provide +5v and ground respectively .Vee is used for controlling LCD contrast.
RS (Register select): There are two very important register inside the LCD.The RS pin is used for their selection. If RS=0, the instruction command code register is selected, allowing the user to send a command such as clear display, cursor etc.If RS=1, the data register is selected allowing the user to send data to be displayed on the LCD.
R/W (read/write): R/W input allows the user to write information to the LCD or read information from it.R/W=1 when reading; R/W=0 when writing.
E (enable): The enable pin is used by the LCD to latch information presented to its data pins.
D0_D7: The 8_bit data pins D0_D7, are used to send information to the LCD or read the contents of the LCD’s internal registers.
Vcc and Vss: Vcc and Vss provide +5v and ground respectively for back light of LCD.
Circuit Description:
The circuit diagram is as shown in the figure 5.1.It consists of five nodes. Each node perform its own function using can protocol. Here port pin 2.0 of microcontroller of each node is connected to can bus.
The AT89C51 microcontroller is the master of the project. it controls the function of the can bus,sensors,switches and visual indicators. The crystal of 12MHz is connected along with the capacitor as shown in the circuit so as to provide the clock to the controller.
Working of each node is explained as follows
Object sensing controller:
Port pin p0.0 of microcontroller is connected to object sensor i.e. SD3443. Whenever it senses the object, sends the data frame with identifier msg2 to dashboard and compressor node to get activate.
Compressor controller:
Port pin p2.2 of microcontroller is connected to led7.whenever it receives the data frame with id msg2 through CAN bus, led7 turn ON which indicates compressor node is activated and it is deactivated when it receives the data frame with id msg6 (LED7 IS OFF).
Temperature controller:
Port 1 of microcontroller is connected to output of ADC to which temperature sensor LM35DZ is connected to read the temperature value.
When temperature node goes on, it starts scanning for data frame with id msg1.when it receives, it starts reading the temperature value of the engine with the help of temperature sensor LM35DZ through 8-bit,8-channel ADC. If temperature exceeds more than 70 degree C, it sends the information to the coolant and dashboard with id msg4.when it receives the remote frame with id msg8, it sends the temperature value to the dashboard and if it receives the remote frame with id msg9, it sends the temperature value to the coolant.
Cooling controller:
Port pin p2.2 of microcontroller is connected to led8.whenever it receives the data frame with id msg4 through CAN bus, led8 turn ON which indicates coolant node is activated. It sends the status of the coolant to the dashboard with id msg5 and whenever temperature goes below 60degree C, led8 goes low which indicates coolant is deactivated
Dashboard controller:
Port pins p1.0, p1.1 and port0 are connected to LCD.port pins from p1.2 to p1.7 is connected to led driver i.e. ULN2803, which consists of Darlington circuit inside so as to drive output signal if it is weak. Port pins from p2.2 to p2.7 is connected to keyboard matrix.
The code is entered using keyboard, if it is correct it send the dataframe with id msg1 to activate all nodes. the status of the compressor i.e. ON or OFF will be received by the dashboard with id msg3 and msg7 respectively which is indicated by led3.similarly, status of the coolant node i.e. ON or OFF will be received by the dashboard with id msg4 and msg9 respectively which is indicated by led5.the temperature readings are received from temperature controller node by sending remote frame with id msg8, which is displayed on LCD.
POWER SUPPLY UNIT:
The power supply unit is as shown in the circuit diagram figure. In the project power supply is designed to give +5V-regulated voltage at the output. The 230V AC is converted into required DC voltage. A step down transformer is placed at the input. This AC voltage is given to rectifier circuit constructed by using bridge rectifier. Electrolyte capacitor of 1000uf is used as filter to give pure DC. IC7805 gives fixed regulated positive voltage of +5V. The regulator output is connected to output terminal.
SOFTWARE
In the can protocol, bus nodes do not have specific address. Instead, the address information is contained in the identifier of the transmitted messages, indicating the message content and priority of the message.
Message configuration.
Msg1: activating all nodes
Msg2: object sensed message
Msg3: status of the compressor node [i.e. ON]
Msg4: exceeded temperature value
Msg5: status of coolant node [i.e. ON]
Msg6: deactivating the compressor node
Msg7: status of compressor node [i.e. OFF]
Msg8: temperature readings for dashboard
Msg9: temperature readings for coolant
Msg10: status of coolant node [i.e. OFF]
Msg11: deactivating all nodes
Today CAN protocol is one of the emerging protocols and is very popular. Its popularity comes only by its features like configuration flexibility, high level of security and economic. It has replaced all point_to_point wiring by one serial bus connecting all control systems.
ADVANTAGES
CAN is low cost protocol devices available driven by high volume production in the automotive and industrial markets.
CAN provides high level security.
Number of nodes not limited by the protocol.
Messages can be sent to either single/multiple nodes.
DISADVANTAGES
It is not permitted for different nodes to send messages with the same identifier as arbitration could fail leading to collisions and errors.
Special bus drivers should be used for longer bus length.
APPLICATIONS
CAN in motor vehicles (cars, trucks, buses) enables communication between ECUs like engine management system, gear control etc.
CAN in industrial automation equipment (control units, sensors and actuators) and for machine control.
CAN in building automation for elevators and escalator control.
CAN in household appliances such as dishwashers, washing machines etc.
CAN in office automation such as document text system i.e., automatic print, sort and bind on demand.
MESSAGES:
Information on the bus is sent in fixed format messages of different but limited length. When the bus is free any connected unit may start to transmit a new message.
INFORMATION ROUTING:
In CAN systems a can node does not make use of any information about the system configuration (e.g. station addresses).this has several important consequences.
SYSTEM FLEXIBILITY:
Nodes can be added to the CAN network without requiring any change in the software or hardware of any node and application layer.
MESSAGE ROUTING:
The content of a message is named by an IDENTIFIER. The identifier does not indicate the destination of the message but describes the meaning of the data ,so that all nodes in the network are able to decide by message filtering whether the data is to be acted upon by them or not.
MULTICAST:
As a consequence of the concept of message filtering any number of nodes can receive and simultaneously act upon the same message.
DATA CONSISTENCY:
Within a CAN network it is guaranteed that a message is simultaneously accepted either by all nodes or by no node. Thus data consistency of a system is achieved by the concepts of multicast and by error handling.
BIT RATE:
The speed of CAN may be different in different systems. However, in a given system the bit rate is uniform and fixed.
PRIORITIES:
The identifier defines a static message priority during bus access.
REMOTE DATA REQUEST:
By sending a remote frame a node requiring data may request another node to send the corresponding data frame. The data frame and the corresponding remote frame named by the same identifier.
MULTIMASTER:
When the bus is free any may start to transmit a message. The unit with the message of highest priority to be transmitted gains bus access.
ARBITRATION:
Whenever the bus is free, any unit may start to transmit a message. If two or more units start transmitting messages at the same time, the bus access conflict is resolved by bit wise arbitration using the identifier. The mechanism of arbitration grantees that neither information nor time is lost. If a data frame and a remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote frame. During arbitration every transmitter compares the level of the bit transmitted with the level that is monitored on the bus. If these levels are equal the unit may continue to send. When a ‘recessive’ level is sent and a ‘dominant’ level is monitored, the unit has lost arbitration and must withdraw without sending one more bit.
SAFETY:
In order to achieve the utmost safety of data transfer, powerful measures for error detection, signaling and self-checking are implemented in every CAN node.
FAULT CONFINEMENT:
CAN nodes are able to distinguish short disturbances from permanent failures. defective nodes are switched off.
CONNECTIONS:
The CAN serial communication link is a bus to which a number of units may be connected. This number has no theoretical limit. Practically the total number of units will be limited by delay and/or electrical loads on the bus line.
BUS VALUES:
The bus can have one of two complementary logical values: ‘dominant’ or ‘recessive’. During simultaneous transmission of ‘dominant’ and ‘recessive’ bits, the resulting bus value will be ‘dominant’. for example, in case of a wired-AND implementation of the bus, the ‘dominant’ level would be represented by a logical ‘0’ and the ‘recessive’ level by a logical ‘1’.
ACKNOWLEDGEMENT:
All receivers check the consistency of the message being received and will acknowledge a consistent message and flag an inconsistent message.
There are two bus states, called "dominant" and "recessive".
The bus logic uses a "Wired-AND" mechanism, that is, "dominant bits" (equivalent to the logic level "Zero") overwrite the "recessive" bits (equivalent to the logic level "One”).
BUS ACCESS AND ARBITRATION
The CAN protocol handles bus accesses according to the concept called “Carrier Sense Multiple Access with Arbitration on Message Priority”. This arbitration concept avoids collisions of messages whose transmission was started by more than one node simultaneously and makes sure the most important message is sent first without time loss.
In the picture above you see the trace of the transmit pins of three bus nodes called A, B and C, and the resulting bus state according to the wired-AND principle.
If two or more bus nodes start their transmission at the same time after having found the bus to be idle, collision of the messages is avoided by bitwise arbitration. Each node sends the bits of its message identifier and monitors the bus level.
At a certain time nodes A and C send a dominant identifier bit. Node B sends a recessive identifier bit but reads back a dominant one. Node B loses bus arbitration and switches to receive mode. Some bits later node C loses arbitration against node A. This means that the message identifier of node A has a lower binary value and therefore a higher priority than the messages of nodes B and C. In this way, the bus node with the highest priority message wins arbitration without losing time by having to repeat the message.
Nodes B and C automatically try to repeat their transmission once the bus returns to the idle state. Node B loses against node C, so the message of node C is transmitted next, followed by node B’s message.
It is not permitted for different nodes to send messages with the same identifier as arbitration could fail leading to collisions and errors.
CAN protocol layers
The intention of their specification is to achieve compatibility between any two CAN Nodes. However, compatibility has different aspects regarding electrical Features and the interpretation of data to be transferred. To achieve design transparency and implementation flexibility CAN has been subdivided into different layers.
The Application layer
The object layer
The transfer layer
The physical layer
The object layer and the transfer layer comprise all services and functions of the data link
layer defined by the ISO / OSI model.
The scope of the object layers includes
Finding which messages are to be transmitted.
Deciding which messages received by the transfer layer is to be used.
Providing an interface to the application layer related hardware
The scope of the transfer layer mainly is the transfer protocol i.e. controlling the framing, performing arbitration, error checking, error signaling, fault confinement, bit timing and synchronization.
The scope of the physical layer is the actual transfer of the bits between the different nodes with respect to all electrical properties.
MESSAGE TRANSFER
Message transfer is manifested and controlled by two frame types.
A DATA FRAME carries data from a transmitter to the receivers. It is composed of seven different bit fields. Start of frame, Arbitration field, control field, data field, crc field, Ack field, End of frame.
Port 1 of microcontroller is connected to output of ADC to which temperature sensor LM35DZ is connected to read the temperature value.
When temperature node goes on, it starts scanning for data frame with id msg1.when it receives, it starts reading the temperature value of the engine with the help of temperature sensor LM35DZ through 8-bit,8-channel ADC. If temperature exceeds more than 70 degree C, it sends the information to the coolant and dashboard with id msg4.when it receives the remote frame with id msg8, it sends the temperature value to the dashboard and if it receives the remote frame with id msg9, it sends the temperature value to the coolant.
Cooling controller:
Port pin p2.2 of microcontroller is connected to led8.whenever it receives the data frame with id msg4 through CAN bus, led8 turn ON which indicates coolant node is activated. It sends the status of the coolant to the dashboard with id msg5 and whenever temperature goes below 60degree C, led8 goes low which indicates coolant is deactivated
Dashboard controller:
Port pins p1.0, p1.1 and port0 are connected to LCD.port pins from p1.2 to p1.7 is connected to led driver i.e. ULN2803, which consists of Darlington circuit inside so as to drive output signal if it is weak. Port pins from p2.2 to p2.7 is connected to keyboard matrix.
The code is entered using keyboard, if it is correct it send the dataframe with id msg1 to activate all nodes. the status of the compressor i.e. ON or OFF will be received by the dashboard with id msg3 and msg7 respectively which is indicated by led3.similarly, status of the coolant node i.e. ON or OFF will be received by the dashboard with id msg4 and msg9 respectively which is indicated by led5.the temperature readings are received from temperature controller node by sending remote frame with id msg8, which is displayed on LCD.
POWER SUPPLY UNIT:
The power supply unit is as shown in the circuit diagram figure. In the project power supply is designed to give +5V-regulated voltage at the output. The 230V AC is converted into required DC voltage. A step down transformer is placed at the input. This AC voltage is given to rectifier circuit constructed by using bridge rectifier. Electrolyte capacitor of 1000uf is used as filter to give pure DC. IC7805 gives fixed regulated positive voltage of +5V. The regulator output is connected to output terminal.
SOFTWARE
In the can protocol, bus nodes do not have specific address. Instead, the address information is contained in the identifier of the transmitted messages, indicating the message content and priority of the message.
Message configuration.
Msg1: activating all nodes
Msg2: object sensed message
Msg3: status of the compressor node [i.e. ON]
Msg4: exceeded temperature value
Msg5: status of coolant node [i.e. ON]
Msg6: deactivating the compressor node
Msg7: status of compressor node [i.e. OFF]
Msg8: temperature readings for dashboard
Msg9: temperature readings for coolant
Msg10: status of coolant node [i.e. OFF]
Msg11: deactivating all nodes
Today CAN protocol is one of the emerging protocols and is very popular. Its popularity comes only by its features like configuration flexibility, high level of security and economic. It has replaced all point_to_point wiring by one serial bus connecting all control systems.
ADVANTAGES
CAN is low cost protocol devices available driven by high volume production in the automotive and industrial markets.
CAN provides high level security.
Number of nodes not limited by the protocol.
Messages can be sent to either single/multiple nodes.
DISADVANTAGES
It is not permitted for different nodes to send messages with the same identifier as arbitration could fail leading to collisions and errors.
Special bus drivers should be used for longer bus length.
APPLICATIONS
CAN in motor vehicles (cars, trucks, buses) enables communication between ECUs like engine management system, gear control etc.
CAN in industrial automation equipment (control units, sensors and actuators) and for machine control.
CAN in building automation for elevators and escalator control.
CAN in household appliances such as dishwashers, washing machines etc.
CAN in office automation such as document text system i.e., automatic print, sort and bind on demand.
MESSAGES:
Information on the bus is sent in fixed format messages of different but limited length. When the bus is free any connected unit may start to transmit a new message.
INFORMATION ROUTING:
In CAN systems a can node does not make use of any information about the system configuration (e.g. station addresses).this has several important consequences.
SYSTEM FLEXIBILITY:
Nodes can be added to the CAN network without requiring any change in the software or hardware of any node and application layer.
MESSAGE ROUTING:
The content of a message is named by an IDENTIFIER. The identifier does not indicate the destination of the message but describes the meaning of the data ,so that all nodes in the network are able to decide by message filtering whether the data is to be acted upon by them or not.
MULTICAST:
As a consequence of the concept of message filtering any number of nodes can receive and simultaneously act upon the same message.
DATA CONSISTENCY:
Within a CAN network it is guaranteed that a message is simultaneously accepted either by all nodes or by no node. Thus data consistency of a system is achieved by the concepts of multicast and by error handling.
BIT RATE:
The speed of CAN may be different in different systems. However, in a given system the bit rate is uniform and fixed.
PRIORITIES:
The identifier defines a static message priority during bus access.
REMOTE DATA REQUEST:
By sending a remote frame a node requiring data may request another node to send the corresponding data frame. The data frame and the corresponding remote frame named by the same identifier.
MULTIMASTER:
When the bus is free any may start to transmit a message. The unit with the message of highest priority to be transmitted gains bus access.
ARBITRATION:
Whenever the bus is free, any unit may start to transmit a message. If two or more units start transmitting messages at the same time, the bus access conflict is resolved by bit wise arbitration using the identifier. The mechanism of arbitration grantees that neither information nor time is lost. If a data frame and a remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote frame. During arbitration every transmitter compares the level of the bit transmitted with the level that is monitored on the bus. If these levels are equal the unit may continue to send. When a ‘recessive’ level is sent and a ‘dominant’ level is monitored, the unit has lost arbitration and must withdraw without sending one more bit.
SAFETY:
In order to achieve the utmost safety of data transfer, powerful measures for error detection, signaling and self-checking are implemented in every CAN node.
FAULT CONFINEMENT:
CAN nodes are able to distinguish short disturbances from permanent failures. defective nodes are switched off.
CONNECTIONS:
The CAN serial communication link is a bus to which a number of units may be connected. This number has no theoretical limit. Practically the total number of units will be limited by delay and/or electrical loads on the bus line.
BUS VALUES:
The bus can have one of two complementary logical values: ‘dominant’ or ‘recessive’. During simultaneous transmission of ‘dominant’ and ‘recessive’ bits, the resulting bus value will be ‘dominant’. for example, in case of a wired-AND implementation of the bus, the ‘dominant’ level would be represented by a logical ‘0’ and the ‘recessive’ level by a logical ‘1’.
ACKNOWLEDGEMENT:
All receivers check the consistency of the message being received and will acknowledge a consistent message and flag an inconsistent message.
There are two bus states, called "dominant" and "recessive".
The bus logic uses a "Wired-AND" mechanism, that is, "dominant bits" (equivalent to the logic level "Zero") overwrite the "recessive" bits (equivalent to the logic level "One”).
BUS ACCESS AND ARBITRATION
The CAN protocol handles bus accesses according to the concept called “Carrier Sense Multiple Access with Arbitration on Message Priority”. This arbitration concept avoids collisions of messages whose transmission was started by more than one node simultaneously and makes sure the most important message is sent first without time loss.
In the picture above you see the trace of the transmit pins of three bus nodes called A, B and C, and the resulting bus state according to the wired-AND principle.
If two or more bus nodes start their transmission at the same time after having found the bus to be idle, collision of the messages is avoided by bitwise arbitration. Each node sends the bits of its message identifier and monitors the bus level.
At a certain time nodes A and C send a dominant identifier bit. Node B sends a recessive identifier bit but reads back a dominant one. Node B loses bus arbitration and switches to receive mode. Some bits later node C loses arbitration against node A. This means that the message identifier of node A has a lower binary value and therefore a higher priority than the messages of nodes B and C. In this way, the bus node with the highest priority message wins arbitration without losing time by having to repeat the message.
Nodes B and C automatically try to repeat their transmission once the bus returns to the idle state. Node B loses against node C, so the message of node C is transmitted next, followed by node B’s message.
It is not permitted for different nodes to send messages with the same identifier as arbitration could fail leading to collisions and errors.
CAN protocol layers
The intention of their specification is to achieve compatibility between any two CAN Nodes. However, compatibility has different aspects regarding electrical Features and the interpretation of data to be transferred. To achieve design transparency and implementation flexibility CAN has been subdivided into different layers.
The Application layer
The object layer
The transfer layer
The physical layer
The object layer and the transfer layer comprise all services and functions of the data link
layer defined by the ISO / OSI model.
The scope of the object layers includes
Finding which messages are to be transmitted.
Deciding which messages received by the transfer layer is to be used.
Providing an interface to the application layer related hardware
The scope of the transfer layer mainly is the transfer protocol i.e. controlling the framing, performing arbitration, error checking, error signaling, fault confinement, bit timing and synchronization.
The scope of the physical layer is the actual transfer of the bits between the different nodes with respect to all electrical properties.
MESSAGE TRANSFER
Message transfer is manifested and controlled by two frame types.
A DATA FRAME carries data from a transmitter to the receivers. It is composed of seven different bit fields. Start of frame, Arbitration field, control field, data field, crc field, Ack field, End of frame.
A REMOTE FRAME is transmitted by a bus unit to request the transmission of the data frame with the same identifier. It is composed of six different bit fields. Start of frame, Arbitration field, control field, crc field, Ack field, End of frame.
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